The present disclosure generally relates to register mapping and, more specifically, to register mapping techniques for virtual systems in which a hypervisor and multiple operating systems operate using of a plurality of hardware threads.
Today, most processors are loaded with hardware functions (e.g., resister mapping) that support virtualization for running a plurality of operating systems (OSs) on a single system. Register mapping is a function for enabling software (e.g., a hypervisor) that administers multiple OSs, or the multiple OSs themselves, to efficiently access registers. An OS that runs on a virtual system is generally referred to as a guest OS or simply an OS. When executing virtualization on a processor without support for register mapping, the hypervisor and the OS share a single register. When there is a transition from the OS operating state to the hypervisor operating state, the content of the single register is shifted to temporary memory, which significantly degrades performance.
To address the performance degradation attributable to shifting the content of the single register between an OS and hypervisor, at least one conventional register mapping technology has provided one register for hypervisor operational use and another register for OS operational use. In this case, hardware automatically determined whether the current operational mode was the hypervisor or the OS and switched the location for a register access using the same register command, as appropriate. Unfortunately, the registers that support register mapping for conventional register mapping technologies are limited and, as such, memory evacuation of the content of unsupported registers is still required at operational switching.
Moreover, known shared processor functions execute shared use of a single processor core with multiple OSs by time-division (or another policy) in order to attain higher functionality through virtualization. However, when the shared processor function is used, register switching occurs between the hypervisor and multiple OSs which further degrades performance. For example, in conventional technologies that implement a shared processor function with a single register assigned for OS use, at the time of a shift between OSs the temporary evacuation of content of the single register degrades performance. Moreover, in systems that implement a multithreading mechanism that provides multiple hardware threads, performance is also degraded because a plurality of hardware threads operate on a single processor core and registers are classified based on which registers can be accessed by each thread. In this case, it is also possible to prepare all the registers for use by each thread, but the register count increases which adversely affects cost and power consumption.
Japanese Laid-Open Publication No. 2009-151650 discloses a computer virtualization device that operates a plurality of OSs within a computer to provide a plurality of virtualized computers. The computer virtualization device provides a memory space identifier on the virtualized computer (i.e., guest register identifier (RID)), a mapping table for administering correspondence of an identifier (physical RID) to be used by the actual computer, an RID converter for referencing the mapping table and converting a guest RID to a physical RID when triggering an emulation process to substitute a guest RID, and an RID table update component for creating a new correspondence and adding it to the mapping table when a correspondence between a guest RID and a physical RID does not exist in the mapping table.